1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a system capable of reducing a difference between the phase of a clock signal and the phase of a data signal, and a method for reducing a skew between a clock signal and a data signal.
2. Description of the Related Art
The prevalence of multimedia applications has demanded enhancement in the operating speed of systems, such as those based on personal computers. Since semiconductor devices play a major role in such enhancement, there has been a long-standing need for increasing the operating speed of semiconductor devices.
In a system including a plurality of semiconductor devices, transfers of signals between devices are required. In order to perform a rapid transfer, recent transfer methods feature a synchronization system, i.e., a clock signal is provided whose level repetitively undergoes transitions In predetermined periods,. so that other signals are synchronized with the clock signal.
FIG. 23A illustrates a conventional synchronization system. A buffer 703a formed on a chip 705 outputs a data signal Data. A buffer 703b formed on a chip 704 receives the date signal Data and outputs it to a holding circuit 701. The holding circuit 701 holds the data signal Data in synchronization with a reference clock signal SysCLK and transfers the data signal Data to an internal circuit 702.
One common method for attaining a higher speed operation in such a synchronization system is increasing the frequency of a reference clock signal. However, there may be a discrepancy or difference in timing between the reference clock signal and another signal (e.g., a data signal). Such a difference in timing is referred to as a skew. A skew may cause an operation failure of the holding circuit.
FIG. 23B describes a mislatching problem due to a shift (hereinafter referred to as a "phase shift") of the phase of a reference clock signal SysCLK relative to the phase of a data signal Data (or vice versa) causing an operation failure of the holding circuit.
FIGS. 24A to 24C illustrate the reasons why a phase shift T becomes more problematic as the frequency of the reference clock signal increases although it is not problematic in the case where the reference clock signal has a sufficiently low frequency.
FIG. 24A illustrates the case where the reference clock signal SysCLK and the data signal completely match in phase.
FIG. 24B illustrates the case where the reference clock signal SysCLK and the data signal have a phase shift T in the case where the reference clock signal SysCLK has a low frequency. The phase shift T in this case is not particularly problematic because nonetheless correct data is being output.
FIG. 24C illustrates the case where the reference clock signal SysCLK and the data signal have a phase shift T in the case where the reference clock signal SysCLK has a high frequency. The phase shift T in this case becomes problematic because correct data is not being output.
Thus, a phase shift exerts a larger influence as each signal is driven faster; this poses an obstacle in realizing a high-speed operation of the overall system.
According to a conventionally employed method for minimizing a phase shift, it is ensured that the transfer path of a reference clock signal is disposed as close to the transfer path of a data signal as possible. However, this method has disadvantages including the limited layout of the signal wiring as well as incapability of accommodating phase shifts due to fluctuation in the supply power and/or fluctuation in temperature.